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WM8756 192khz, six channel sacd? compatible audio dac wolfson microelectronics ltd www.wolfsonmicro.com advanced information june 2002, rev 2.0 copyright ? 2002 wolfson microelectronics ltd . description the WM8756 is a high performance 6-channel dac designed for audio applications such as sacd? players, dvd-v and dvd-a, home audio and theatre systems. the device supports data input word lengths from 16 to 32-bits and sampling rates up to 192khz. the WM8756 can implement 2 or 6 channels at 192khz for high-end dvd- audio, or 6 channels at up to 192khz for surround applications. additionally 64x dsd bitstream support is offered on all 6 channels. the WM8756 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 dacs in a 48-pin tqfp package. the WM8756 also includes a digitally controllable mute and attenuator function on each channel, accessible during pcm operation. an on-chip multiplexer selects between pcm or dsd audio data input pins. the WM8756 supports hardware or software connection schemes for audio dac control. the serial control interface provides access to a wide range of features including on- chip mute, attenuation and phase reversal. hardware pin- controllable operation is also available. the WM8756 is an ideal device for all surround sound applications supporting the sacd? audio format, such as sacd players, multi-format players and home entertainment systems. features ? 6-channel dac with pcm or bitstream (dsd) operation. ? dsd 64x bitstream support for super audio cd? ? independent input pins for pcm and dsd data with on- chip multiplexer ? thd ?96db, snr 106db (?a? weighted @ 48khz) ? pcm mode sampling rate: 8khz ? 192khz ? master or slave operation with normal or phase modulation method of dsd data transfer ? 3-wire serial control interface ? programmable pcm audio data interface modes ? i 2 s, left, right justified or dsp ? 16/20/24/32 bit word lengths ? independent digital volume control on each channel with 127.5db range in 0.5db steps (in pcm mode) ? 3.0v ? 5.5v supply (3.3v digital / 5v analogue option) ? 48-pin tqfp package applications ? super audio cd (sacd?) players ? universal and multi-format disc players ? home theatre systems block diagram control interface digital filters sigma delta modulator sigma delta modulator mux mux pcm/dsd digital filters sigma delta modulator sigma delta modulator mux mux pcm/dsd digital filters sigma delta modulator sigma delta modulator mux mux pcm/dsd audio interface pcm data dsd data low pass filter low pass filter right dac left dac bckin dsd4 dsd3 dsd2 dsd1 dsd0 dsdclk64 din2 din1 din0 lrcin dsdclk128 dsd5 csb dmcksel dmslv mute mode scki dsdb md/dm mc/iwl ml/i2s out0r out2l gr2 out2r out1l gr1 out1r out0l gr0 low pass filter low pass filter right dac left dac low pass filter low pass filter right dac left dac agnd3 dgnd avdd1 agnd1 avdd2 agnd2 dvdd lrcin2
WM8756 advanced information ai rev 2.0 june 2002 2 pin configuration ordering information device temp. range package WM8756eft -25 to +85 o c 48-pin tqfp nc nc avdd2 cap ml/i2s dsdb dgnd mc/iwl md/dm din1 dsd4 dsd3 dsd2 dsd1 dsd0 din2 dsd5 dsdclk64 mode din0 dmcksel dvdd scki bckin lrcin nc nc avdd1 nc dmslv out0r out1l gr1 out1r agnd3 out0l gr0 out2l gr2 out2r agnd1 1 9 8 7 6 5 4 3 2 11 10 16 17 18 19 20 21 22 13 14 15 31 30 29 28 27 26 33 32 44 43 42 41 40 39 38 12 37 36 35 34 25 24 23 lrcin2 dsdclk128 csb 48 47 46 45 mute agnd2 nc nc
WM8756 advanced information ai rev 2.0 june 2002 3 pin description pin name type description 1 din1 digital input channel 1 serial audio data input in pcm mode. 2 din2 digital input channel 2 serial audio data input in pcm mode. 3 dsd0 digital input p.d. channel 0 left dsd format audio data input 4 dsd1 digital input p.d. channel 0 right dsd format audio data input 5 dsd2 digital input p.d. channel 1 left dsd format audio data input 6 dsd3 digital input p.d. channel 1 right dsd format audio data input 7 dsd4 digital input p.d. channel 2 left dsd format audio data input 8 dsd5 digital input p.d. channel 2 right dsd format audio data input 9 dsdclk64 digital in/out dsd format data clock at 64fs 10 dsdclk128 digital in/out dsd format data clock at 128fs (used in ? modulated data ? mode) 11 mode digital input control method selection pin in pcm mode. ? lo ? = software mode 12 mute digital in/out mute control pin in pcm mode. ? lo ? = not muted 13 lrcin2 digital input p.d. second lrcin input for dual rate mode 14 dsdb digital input p.u. dsd or pcm audio data format select; ? lo ? = dsd mode, ? hi ? = pcm mode 15 dgnd supply digital gnd 16 ml/i2s digital input p.u. software mode: in 3-wire serial control mode, latch input. hardware mode: input format selection: 17 mc/iwl digital input p.u. software mode: in 3-wire serial control mode, clock input. hardware mode: input word length selection: 18 md/dm digital input software mode: in 3-wire serial control mode, data input. hardware mode: de-emphasis selection 19 csb digital input p.d. 3-wire serial port chip select ? active low 20 n.c. n.c. no internal connection 21 avdd2 supply analogue positive dac reference 22 n.c. n.c. no internal connection 23 cap analogue output analogue internal mid-rail reference de-coupling point 24 n.c. n.c. no internal connection 25 out2l analogue output left channel 2 output. 26 gr2 analogue input channel 2 negative reference. 27 out2r analogue output right channel 2 output. 28 agnd1 supply analogue gnd 29 agnd2 supply analogue gnd 30 out1l analogue output left channel 1 output. 31 gr1 analogue input channel 1 negative reference. 32 out1r analogue output right channel 1 output. 33 agnd3 supply analogue gnd 34 out0l analogue output left channel 0 output. 35 gr0 analogue input channel 0 negative reference. 36 out0r analogue output right channel 0 output. 37-39 nc nc no internal connection 40 avdd1 supply analogue positive supply 41 nc nc no internal connection 42 dmslv digital input p.d. dsd mode master or slave operation select; ? lo ? = slave (clocks are i nput) 43 dmcksel digital input p.d. dsd master mode clock select (lo for 256fs; hi for 384fs) 44 dvdd supply digital positive supply. 45 scki digital input master clock input 46 bckin digital input audio data bit clock input. 47 lrcin digital input dac sample rate clock input in pcm mode 48 din0 digital input channel 0 serial audio data input in pcm mode. note - digital input pins have schmitt trigger input buffers. pins marked ? p.u. ? or ? p.d. ? have internal pull-up or pull down.
WM8756 advanced information ai rev 2.0 june 2002 4 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 37mhz operating temperature range, t a -25 c +85 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c lead temperature (soldering 10 seconds) +240 c lead temperature (soldering 2 minutes) +183 c
WM8756 advanced information ai rev 2.0 june 2002 5 dc electrical characteristics parameter symbol test conditions min typ max unit digital supply range dvdd 3.0 5.5 v analogue supply range avdd 3.0 5.5 v ground agnd, dgnd 0 v difference of dgnd to agnd -0.3 0 +0.3 v difference of gr to agnd -0.3 0 +0.3 v analogue supply current avdd = 5v 58 ma digital supply current dvdd = 5v 22 ma analogue supply current avdd = 3.3v 57 ma digital supply current dvdd = 3.3v 11 ma analogue supply current power down, stop clock 0.4 ma digital supply current power down, stop clock 0.09 ma note : 1. avdd must at all times be equal or greater than dvdd. dvdd = 3v, avdd = 5v is allowed. 2. where used avdd represents avdd1 = avdd2, agnd represents agnd1 = agnd2 = agnd3 and gr represents gr0 = gr1 = gr2. ac electrical characteristics test conditions avdd = dvdd = 3v, agnd = 0v = dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol = 2ma 0.4 v output high v oh i oh = 2ma 2.4 v analogue reference levels reference voltage v cap avdd2 ? gr2/2 v potential divider resistance r cap 25k ohms dac output (load = 10k ohms. 50pf) 0dbfs full scale output voltage at dac outputs 1.1 x avdd1/5 v rms snr (note 1,2,3) a-weighted, @ fs = 48khz 100 106 db snr (note 1,2,3) a-weighted @ fs = 96khz 98 105 db snr (note 1,2,3) a-weighted @ fs = 192khz 105 db snr (note 1,2,3) a-weighted, @ fs = 48khz avdd=dvdd=3.3v 103 db snr (note 1,2,3) a-weighted @ fs = 96khz avdd=dvdd=3.3v 103 db snr (note 1,2,3) non ? a ? weighted @ fs = 48khz avdd=dvdd=5v 103 db thd (note 1,2,3) 1khz, 0dbfs -90 -95 db thd+n (dynamic range, note 2) 1khz, -60dbfs 100 -106 db dac channel separation <95 db
WM8756 advanced information ai rev 2.0 june 2002 6 test conditions avdd = dvdd = 3v, agnd = 0v = dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit analogue output levels load = 10k ohms, 0dbfs 1.1 v rms output level load = 10k ohms, 0dbfs, (avdd = 3.3v) 0.73 v rms gain mismatch channel-to-channel 1 %fsr to midrail or a.c. coupled 1 kohms minimum resistance load to midrail or a.c. coupled (avdd = 3.3v) 1 kohms maximum capacitance load 5v or 3.3v 100 pf output d.c. level avdd1- agnd/2 v power on reset (por) por threshold 2.0 v notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ? a ? weighted over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. cap decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance).
WM8756 advanced information ai rev 2.0 june 2002 7 digital filter characteristics parameter symbol test conditions min typ max unit passband 0.05 db 0.444fs db stopband -3db 0.487fs passband ripple 0.05 db stopband attenuation f > 0.555fs -60 db sacd filter characteristics with 64fs dsd data where fs = 44.1ks/s. response filter response without post- filter filter response with 3 rd order butterworth post-filter (-3db at 55khz) pass band peak ripple 0.017db 0.017db attenuation at 20khz -0.012db -0.021db attenuation at 50khz -2.3db -3.9db attenuation at 100khz -15.5db -31db terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with n o signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple - any variation of the frequency response in the pass-band region.
WM8756 advanced information ai rev 2.0 june 2002 8 master clock timing scki t sckil t sckih t sckiy figure 1 master clock timing requirements test conditions avdd = dvdd = 5v, agnd = gr = dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information scki system clock pulse width high t sckih 13 ns scki system clock pulse width low t sckil 13 ns scki system clock cycle time t sckiy 26 ns scki duty cycle 40:60 60:40 table 1 master clock timing requirements digital audio interface timing bckin din0/1/2 lrcin t bch t bcl t bl t lb t bcy t ds t dh figure 2 pcm digital audio data timing test conditions avdd = dvdd = 5v, agnd = gr = dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 40 ns bckin pulse width high t bch 16 ns bckin pulse width low t bcl 16 ns lrcin set-up time to bckin rising edge t lb 8 ns lrcin hold time from bckin rising edge t bl 8 ns din0/1/2 set-up time to bckin rising edge t ds 8 ns din0/1/2 hold time from bckin rising edge t dh 8 ns table 2 pcm digital audio timing
WM8756 advanced information ai rev 2.0 june 2002 9 dsd audio monophase interface dsdclk64 dsd[0:5] t dcl t dch t dcy t ds t dh figure 3 dsd audio data timing ? normal mode test conditions avdd = dvdd = 5v, agnd = gr = dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information dsdclk64 cycle time t dcy 354.4 ns dsdclk64 pulse width high t dch 80 ns dsdclk64 pulse width low t dcl 80 ns dsd[5:0] set-up time to dsdclk64 rising edge t ds 10 ns dsd[5:0] hold time from dsdclk64 rising edge t dh 10 ns table 3 dsd audio data timing ? normal mode
WM8756 advanced information ai rev 2.0 june 2002 10 dsd audio biphase interface dsdclk128 dsd[0:5] t bdch t bdcy128 t bds d(n) inverse d(n) t bdh dsdclk64 inverse d(n-1) t diff t bdcl t bdcy64 figure 4 dsd audio data timing - phase modulation mode test conditions avdd= dvdd = 5v, agnd= gr= dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information dsdclk64 cycle time t bdcy64 354.4 ns dsdclk128 cycle time t bdcy128 177.2 ns dsdclk128 pulse width high t bdch 80 ns dsdclk128 pulse width low t bdcl 80 ns dsd[0:5] set-up time to dsdclk128 rising edge t bds 10 ns dsd[0:5] hold time from dsdclk128 rising edge t bdh 10 ns difference in edge timing of dsdclk64 to dsdclk128 t diff 20 ns table 4 dsd digital audio timing
WM8756 advanced information ai rev 2.0 june 2002 11 digital control interface timing ml/i2s mc/iwl md/dm t mll t dho t dsu t mlh t mcy t mch t mcl t scs lsb t css figure 5 control interface input timing: 3-wire serial control mode test conditions avdd= dvdd = 5v, agnd= gr= dgnd = 0v, t a = +25 o c, fs = 48khz, scki = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information mc/iwl rising edge to ml/i2s rising edge t scs 60 ns mc/iwl pulse cycle time t mcy 80 ns mc/iwl pulse width low t mcl 20 ns mc/iwl pulse width high t mch 20 ns md/dm to mc/iwl set-up time t dsu 20 ns mc/iwl to md/dm hold time t dho 20 ns ml/i2s pulse width low t mll 20 ns ml/i2s pulse width high t mlh 20 ns ml/i2s rising to mc/iwl rising t css 20 ns table 5 control interface input timing information
WM8756 advanced information ai rev 2.0 june 2002 12 device description introduction WM8756 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo dac and output smoothing filters. the device is implemented as three separate stereo dacs in a single package and controlled by a single interface. each dac has its own data input din0/1/2, and lrcin, bckin and scki are shared between them. additionally dsd compatible bitstream operation at 64x oversampling is supported on all 6 channels. selection of normal pcm operation or this additional dsd mode is determined by the input level on the dsdb pin (14). control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). the mode pin selects between hardware and software control. in software control mode, a 3 wire spi type interface is used. this interface may be asynchronous to the audio data interface. control data will be re-synchronized to the audio processing internally. operation using a system clock of 256fs, 384fs or 512fs is provided, selection between clock rates being automatically controlled in hardware mode, or serially controlled when in software mode. sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. support is also provided for up to 192ks/s using a system clock of 128fs or 192fs. in normal pcm mode, the audio data interface supports right, left and i 2 s (philips left justified, one bit delayed) interface formats along with a highly flexible dsp serial port interface. when in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (i 2 s or right justified), input word length (16, 20, 24, or 32-bit) and de-emphasis functions. in dsd mode, a separate bitstream data input pin is required for each of the 6 channels, plus a 64fs dataclock dsdclk64. these signals are applied via separate pins (pins 3-9) and the signals multiplexed internally into the dac circuits, under control of the dsdb mode select pin (14). additionally in dsd mode, a phase modulation scheme is supported, where the audio data is transmitted as a manchester type, bi-phase encoded bitstream. this has the advantage of removing the significant audio spectral energy from the datastream, so minimising digital signal corruption of the analogue outputs. in order to simplify decoding of this phase modulated data, a 2x speed clock (dsdclk128) is used to sample the incoming data. this ? modulated ? mode is auto-detected from the presence of a clock signal on the dsdclk128 pin. in dsd mode, clocks for the dac can be inputs (WM8756 in sl ave m ode) or outputs (WM8756 in master mode). when clocks are outputs, scki remains an input, the lower rate clocks being derived by dividing this master clock signal. depending upon the setting on the dmcksel pin, a master clock of either 256fs or 384fs may be used as input, from which the dsd clocks will be derived appropriately. audio data sampling rates in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system ? s master clock. the external master system clock can be applied directly through the scki input pin with no software configuration necessary. note that on the WM8756, scki is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. the system clock for WM8756 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (lrcin) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the system clock is used to operate the digital filters and the noise shaping circuits. the WM8756 has a system clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 system clocks). if greater than 32 clocks error, the interface switches to 768fs and holds the output at the level of the last sample. the system clock should be synchronised with lrcin, although the WM8756 is tolerant of phase differences or jitter on this clock. table 6 shows the typical system clock frequency inputs for the WM8756.
WM8756 advanced information ai rev 2.0 june 2002 13 system clock frequency (mhz) sampling rate (lrcin) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.114 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 6 system clock frequencies versus sampling rate dsd mode when pin 14, dsdb pin is held low, the device is reconfigured to operate as a dsd or ? bitsteam ? compatible dac. that is, the input audio data is in a sigma delta modulated form, or pulse density modulated. in this case the only signals required are the bitstream for each channel supported, and the oversampling clock. WM8756 supports this mode when run at a 64x oversample rate. that is, the bitstream data is supplied at a rate of 64 bits per normal word clock. of course no word clock is provided, and the actual spectral content of the data is determined by the noise shaping that was used to create the bitstream. WM8756 can support six channels of bitstream or dsd audio. data bitstreams and the 64fs clock are applied to pins 3-9 and 10, if the dsdclk128 pin is used. signals applied to the pcm input pins 1,2, 45-48 are ignored. the dsdb signal controls an internal multiplexor which switches the signals on the dsd input pins into the dac rather than the pcm signals. in dsd mode operation, the entire digital filter on WM8756 is disabled, and the bitstream data is applied directly to the multi-bit switched capacitor dac ? s in the analogue part of the device. there, rather than operate as oversampled multi bit dacs, the dac inputs are reconfigured to act as analogue fir filters, so providing both d to a conversion of the bitstream data, and analogue smoothing of the sampled waveform with no phase distortion. filter responses of the analogue filter that results are shown in figure 26 - figure 29. note in dsd mode software controlled functions such as digital volume control and phase reversal, are not available. the fir filter response is designed such that by adding only a 3 rd order butterworth type post dac filter, which may be implemented with a single op-amp, the scarlet book specified filter requirements may be met, saving cost over the 5 th order filter normally needed. it is normally desirable to use an external analogue post-dac filter, particularly in the case of dsd operation due to the presence of high frequency energy as a result of the aggressive high order noise shaping used in the creation of the modulated dsd datastream. the analogue fir filter used in WM8756 provides useful filtering of this noise, but it may be desirable to add further post filtering using active rc filters. figure 26 - figure 29 show the overall filter response of the combined dac filter operating in dsd mode with an external 3 th order butterworth active rc post-dac filter. pcm digital audio interface pcm audio data is applied to the internal dac filters via the pcm digital audio interface. 5 popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp early mode ? dsp late mode all 5 formats send the msb first and support word lengths of 16, 20, 24 and 32 bits except that 32 bit data is not supported in right justified mode. din0/1/2 and lrcin are sampled on the rising, or falling edge of bckin. in left justified, right justified and i 2 s modes, the digital audio interface receives data on the din0/1/2 inputs. audio data for each stereo channel is time multiplexed with lrcin indicating whether the left or right channel is present. lrcin is also used as a timing reference to indicate the beginning or end of the data words.
WM8756 advanced information ai rev 2.0 june 2002 14 in left justified, right justified and i 2 s modes, the minimum number of bckins per lrcin period is 2 times the selected word length. lrcin must be high for a minimum of word length bckins and low for a minimum of word length bckins. any mark to space ratio on lrcin is acceptable provided the above requirements are met. the WM8756 will automatically detect when data with a lrcin period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. word length will revert to the previously programmed value if a lrcin period other than 32 is detected. in dsp early or dsp late mode, all 6 channels are time multiplexed onto din0. lrcin is used as a frame sync signal to identify the msb of the first word. the minimum number of bckins per lrcin period is 6 times the selected word length. any mark to space ratio is acceptable on lrcin provided the rising edge is correctly positioned (see figures 9 and 10). left justified mode in left justified mode, the msb is sampled on the first rising edge of bckin following a lrcin transition. lrcin is high during the left samples and low during the right samples. left channel right channel lrcin bckin din0/1/2 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 6 left justified mode timing diagram right justified mode in right justified mode, the lsb is sampled on the rising edge of bckin preceding a lrcin transition. lrcin is high during the left samples and low during the right samples. left channel right channel lrcin bckin din0/1/2 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 7 right justified mode timing diagram
WM8756 advanced information ai rev 2.0 june 2002 15 i 2 s mode in i 2 s mode, the msb is sampled on the second rising edge of bckin following a lrcin transition. lrcin is low during the left samples and high during the right samples. left channel right channel lrcin bckin din0/1/2 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bckin 1 bckin figure 8 i 2 s mode timing diagram dsp early mode in dsp early mode, the first bit is sampled on the bckin edge following the one which detects a low to high transition on lrcin. 1 bckin lrcin bckin din0 input word length (iwl) 1/fs channel 0 left n 2 1 n-1 lsb msb n 2 1 n-1 channel 0 right 2 1 channel 1 left n n-1 channel 2 right no valid data 1 bckin figure 9 dsp early mode timing diagram dsp late mode in dsp late mode, the first bit is sampled on the bckin edge which detects a low to high transition on lrcin. lrcin bckin din0 input word length (iwl) 1/fs channel 0 left n 2 1 n-1 lsb msb n 2 1 n-1 channel 0 right 2 1 channel 1 left n n-1 channel 2 right no valid data 1 figure 10 dsp late mode timing diagram in both early and late dsp modes, dac0 left is always sent first, followed immediately by data words for the other 5 channels. no bckin edges are allowed between the data words. the word order is dac0 left, dac0 right, dac1 left, dac1 right, dac2 left, dac2 right.
WM8756 advanced information ai rev 2.0 june 2002 16 split rate mode the WM8756 can be used with differing sample rates on the front and rear channels. this allows extremely high quality audio to be played on the front two channels whilst the other channels use normal high quality data streams. this mode will only work with a front data rate of 192khz and a rear rate of 96khz but can be used with all the normal data formats except the two dsp modes and with the system at either 128fs or 192fs see figure 11. when running in split rate mode all the channels are clocked in using a common bckin; the front channels using lrcin and all the other channels using lrcin2 see figure 11. left channel right channel lrcin bckin din0 2/fs lsb msb lsb msb left channel right channel n 2 1n 2 1n 2 1n 2 1 lsb msb lsb msb n 2 1 n 2 1 msb lsb lsb msb din1/2 lrcin2 left channel right channel figure 11 split rate audio mode timing diagram notes: 1. figure 11 shows the timing for left justified. however, this is similar for right justified and i2s. 2. the edges of lrcin and lrcin2 must be coincidental.
WM8756 advanced information ai rev 2.0 june 2002 17 modes of operation control of the various modes of operation for the WM8756 is either by software control over the serial interface, or by hard- wired pin control. selection of software or hardware mode is via the mode pin. the following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. note : in dsd mode, the control interface is available but none of the functions will have any effect except the pdwn bit because the dsd data by-passes the majority of the signal processing. function options software control default value pin 11: mode = 0 hardware control behaviour pin 11: mode = 1 input audio data format right justified left justified i 2 s format dsp formats fmt = 00 (default) fmt = 01 fmt = 10 fmt = 11 pin 16, 17: ml/i2s, mc/iwl = 00, 01 or 10 not available in hardware mode pin 16, 17: ml/i2s, mc/iwl = 11 not available in hardware mode input word length 16 20 24 32 iwl[1:0] = 00 iwl[1:0] = 01 iwl[1:0] = 10 (default) iwl[1:0] = 11 pin 16, 17: ml/i2s, mc/iwl = 00 (rj) pin 16, 17: ml/i2s, mc/iwl = 01 (rj) pin 16, 17: ml/i2s, mc/iwl = 10 (rj) pin 16, 17: ml/i2s, mc/iwl = 11 (i 2 s) de-emphasis selection on off deemph = 1 deemph = 0 (default) pin 18: md/dm = 1 pin 18: md/dm = 0 mute on off mute = 1 mute = 0 (default) pin 12: mute = 1 pin 12: mute = 0 input lrcin polarity normal inverted lrp = 0 (default) lrp = 1 not available in hardware mode, default value set volume control lch, rch individually lch, rch common atc = 0; 0db (default) atc = 1 not available in hardware mode, gain defaults to 0db infinite zero detect on off izd = 1 izd = 0 (default) automute function controlled from mute pin low = never mute floating = automute enable high = mute power down chip on chip off pdwn = 0 (default) pdwn = 1 run scki stop scki dac output control see table 8 for all options default is pl[3:0] = 1001, stereo mode not available in hardware mode table 7 control function summary
WM8756 advanced information ai rev 2.0 june 2002 18 software control modes digital audio interface control registers interface format is selected via the fmt[1:0] register bits: register address bit label default description 0000011 interface control 1:0 fmt[1:0] 00 interface format select 00 : right justified mode 01: left justified mode 10: i2s mode 11: dsp (early or late) mode in left justified, right justified or i2s modes, the lrp register bit controls the polarity of lrcin. if this bit is set high, the expected polarity of lrcin will be the opposite of that shown in figure 6, figure 7 and figure 8. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. register address bit label default description 0000011 interface control 2 lrp 0 lrcin polarity 0 : normal lrcin polarity 1: inverted lrcin polarity in dsp modes, the lrcin register bit is used to select between early and late modes: register address bit label default description 0000011 interface control 2 lrp 0 dsp format 0 : early dsp mode 1: late dsp mode by default, lrcin and din0/1/2 are sampled on the rising edge of bckin and should ideally change on the falling edge. data sources which change lrcin and din0/1/2 on the rising edge of bckin can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bckin to the inverse of that shown in figures 6, 7 and 8. register address bit label default description 0000011 interface control 3 bcp 0 bckin polarity 0 : normal bckin polarity 1: inverted bckin polarity the iwl[1:0] bits are used to control the input word length. register address bit label default description 0000011 interface control 5:4 iwl[1:0] 10 input word length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data note: if 32-bit mode is selected in right justified mode, the WM8756 defaults to 24 bits. in all modes, the data is signed 2 ? s complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the WM8756 pads the unused lsbs with zeros. if the dac is programmed into 32 bit mode, the 8 lsbs are ignored.
WM8756 advanced information ai rev 2.0 june 2002 19 the rev[2:0] bits are used to invert the phase of the dac outputs. rev0 controls phase of dac0, rev1 controls phase of dac1 and rev2 controls phase of dac2. register address bit label default description 0000011 interface control 8:6 rev[2:0] 000 output phase direction 1 in bit 6 reverses out0l/r. 1 in bit 7 reverses out1l/r. 1 in bit 8 reverses out2l/r. mute modes setting the mute register bit will apply a ? soft ? mute to the input of the digital filters: register address bit label default description 0000010 dac channel control 0 mute 0 soft mute select 0 : normal operation 1: soft mute all channels -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s) figure 12 application and release of soft mute figure 12 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v cap with a time constant of approximately 64 input samples. if mute is applied for 1024 or more input samples, the outputs will be connected directly to v cap - this feature can be disabled using the izd (infinite zero detect) bit. when mute is de-asserted, the output will restart almost immediately from the current input sample. note that all other means of muting the dac channels (setting the pl[3:0] bits to 0, setting the pdwn bit or setting attenuation to 0) will cause much more abrupt muting of the output. setting the izd register bit will enable the internal analogue mute feature: register address bit label default description 0000010 dac channel control 4 izd 0 internal analogue mute disable 0 : disable analogue mute 1: enable analogue mute
WM8756 advanced information ai rev 2.0 june 2002 20 with izd enabled, applying mute for 1024 consecutive input samples will cause all outputs to be connected directly to v cap . additionally, if 2048 consecutive zero input samples are applied to all 6 channels, and izd=0, internal analogue mute will be applied. it will be removed as soon as any channel receives a non-zero input. the mute pin can be used as an input. in this case it performs the same function as the mute register bit. driving the mute pin high will apply a ? soft ? mute. driving it low again, will remove the mute immediately. note that this hardware mute feature doesn ? t require the mode pin to be set high. mute pin description 0 normal operation 1 mute all dac channels floating mute becomes an output to indicate when izd occurs. h=izd detected (mute enabled), l=izd not detected (mute disabled). a diagram showing how the various mute modes interact is shown below in figure 13. izd (register bit) automuted (internal signal) 10k : mu (register bit) softmute (internal signal) mute pin figure 13 selection logic for mute modes the mute pin behaves as a bi-directional function that is, as an input to select mute or not-mute, or as an output indication of automute operation. mute is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. taking mute low again allows data into the filter. the automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. after such an event, a latch is set whose output (automuted) is wire or ? ed through a 10kohm resistor to the mute pin. thus if the mute pin is not being driven, the automute function will assert mute. if mute is tied low, automuted is overridden and will not mute. if mute is driven from a source follower, or diode, then both mute and automute functions are available. if mute is not driven, automuted appears as a weak output (10k source impedance) so can be used to drive external mute circuits. the automute signal is and ? ed with izd, this qualified mute signal then being or ? ed into the softmute control. therefore, in software mode, automute operation may be controlled with izd control bit.
WM8756 advanced information ai rev 2.0 june 2002 21 de-emphasis mode setting the deemph register bit puts the all the digital filters into de-emphasis mode: register address bit label default description 0000010 dac channel control 1 deemph 0 de-emphasis mode select: 0 : normal mode 1: de-emphasis mode refer to figure 20 - figure 25 for details of the de-emphasis filtering effects at different sample rates. in hardware mode (mode=1) driving the md/dm pin high has the same effect as setting the deemph bit: mode pin md/dm pin description 0 ignored de-emphasis controlled from deemph register bit 1 0 normal mode 1 1 de-emphasis mode powerdown mode setting the pdwn register bit immediately connects all outputs to v cap and selects a low power mode. all trace of the previous input samples is removed, but all control register settings are preserved. when pdwn is cleared again the first 16 input samples will be ignored as the fir will repeat it ? s power-on initialisation sequence. register address bit label default description 0000010 dac channel control 2 pdwn 0 power down mode select: 0 : normal mode 1: power down mode attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channels for all three pairs of dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. register address bit label default description 0000010 dac channel control 3 atc 0 attenuator control mode: 0 : right channels use right attenuations 1: right channels use left attenuations
WM8756 advanced information ai rev 2.0 june 2002 22 dac output control the dac output control word determines how the left and right inputs to the audio interface are applied to the left and right dacs: register address bit label default description pl[3:0] left output right output 0000 mute mute 0001 left mute 0010 right mute 0011 (l+r)/2 mute 0100 mute left 0101 left left 0110 right left 0111 (l+r)/2 left 1000 mute right 1001 left right 1010 right right 1011 (l+r)/2 right 1100 mute (l+r)/2 1101 left (l+r)/2 1110 right (l+r)/2 0000010 dac control 8:5 pl[3:0] 1001 1111 (l+r)/2 (l+r)/2 table 8 input to output control
WM8756 advanced information ai rev 2.0 june 2002 23 attenuation control (only applicable to pcm mode) each dac channel can be attenuated digitally before being applied to the digital filter. attenuation is 0db by default but can be set between 0 and 127.5db in 0.5db steps using the 7 attenuation control words. all attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. setting the update bit on any attenuation write will cause all pre-latched values to be immediately applied to the dac channels. a master attenuation register is also included, allowing all attenuations to be set to the same value in a single write. register address bit label default description 7:0 l0a[7:0] 11111111 (0db) attenuation level of left channel dacl0 in 0.5db steps, see table 10 attenuation control levels. 0000 attenuation dacl0 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl0 in intermediate latch (no change to output) 1: store dacl0 and update attenuation on all channels. 7:0 r0a[7:0] 11111111 (0db) attenuation level of right channel dacr0 in 0.5db steps, see table 10 attenuation control levels. 0001 attenuation dacr0 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr0 in intermediate latch (no change to output) 1: store dacr0 and update attenuation on all channels. 7:0 l1a[7:0] 11111111 (0db) attenuation level of left channel dacl1 in 0.5db steps, see table 10 attenuation control levels. 0100 attenuation dacl1 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl1 in intermediate latch (no change to output) 1: store dacl1 and update attenuation on all channels. 7:0 r1a[7:0] 11111111 (0db) attenuation level of right channel dacr1 in 0.5db steps, see table 10 attenuation control levels. 0101 attenuation dacr1 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr1 in intermediate latch (no change to output) 1: store dacr1 and update attenuation on all channels. 7:0 l2a[7:0] 11111111 (0db) attenuation level of left channel dacl2 in 0.5db steps, see table 10 attenuation control levels. 0110 attenuation dacl2 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl2 in intermediate latch (no change to output) 1: store dacl2 and update attenuation on all channels. 7:0 r2a[7:0] 11111111 (0db) attenuation level of right channel dacr2 in 0.5db steps, see table 10 attenuation control levels. 0111 attenuation dacr2 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr2 in intermediate latch (no change to output) 1: store dacr2 and update attenuation on all channels. 7:0 masta[7:0] 11111111 (0db) attenuation of all channels in 0.5db steps, see table 10 attenuation control levels. 1000 master attenuation (all channels) 8 update not latched controls simultaneous update of all attenuation latches 0: store masta[7:0] in all intermediate latches (no change) 1: store masta[7:0] and update attenuation on all channels. table 9 attenuation register map notes : 1. the update bit is not latched. if update=0, the attenuation value will be written to the pre-latch but not applied to the relevant dac. if update=1, all pre-latched values will be applied from the next input sample. writing to masta[7:0] overwrites any values previously sent to l0a[7:0], l1a[7:0], l2a[7:0], r0a[7:0], r1a[7:0], r2a[7:0]. 2. the attenuation level is only applied when the input data passes through midrail unless the zcd function (register 9, bit 1) is disabled where it will change immediately.
WM8756 advanced information ai rev 2.0 june 2002 24 dac output attenuation register bits [7:0] of l0a and r0a control the left and right channel attenuation of dac 0. register bits [7:0] of l1a and r1a control the left and right channel attenuation of dac 1. register bits [7:0] of l2a and r2a control the left and right channel attenuation of dac 2. register bits [7:0] of masta are a register that can be used to control attenuation of all channels. table 15 shows how the attenuation levels are selected from the 8-bit words. ax[7:0] attenuation level 00(hex) - db (mute) 01(hex) -127.5db : : : : : : fe(hex) -0.5db ff(hex) 0db table 10 attenuation control levels extended interface control it is possible to run the WM8756 channels at different rates with the front two channels running at twice the rate of the rear four channels. in this mode which is enabled by bit 0 of register 9, the interface runs at the faster data rate but pin 13 acts as the framing lrcin for the rear channels see figure 11. register address bit label default description 0001001 split rate mode 0 2spd 0 activates the split rate mode 0: normal operation. 1: split rate operation. when the WM8756 receives updates to the volume levels it will, by default, wait for the signal to pass through midrail before applying the change to the output. this ensures that minimal distortion is seen on the output when the volume is changed. this function applies individually to each channel. register address bit label default description 0001001 zero crossing detect 1 zcd 0 controls the zcd 0: enabled. 1: disabled.
WM8756 advanced information ai rev 2.0 june 2002 25 hardware control modes when the mode pin is held high, and dsdb pin is high, the following hardware modes of operation are available. mute and automute operation in both hardware and software modes pin 12 (mute) controls selection of mute directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. automuted (internal signal) 10k : softmute (internal signal) mute pin figure 14 mute circuit operation the mute pin behaves as a bi-directional function, that is, as an input to select mute or not-mute, or as an output indication of automute operation. mute is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. taking mute low again allows data into the filter. the automute function detects a series of zero value audio samples of 1024 samples long being applied to all 6 channels. after such an event, a latch is set whose output (automuted) is wire or ? ed through a 10kohm resistor to the mute pin. thus if the mute pin is not being driven, the automute function will assert mute. if mute is tied low, automuted is overridden and will not mute. if mute is driven from a source follower, or diode, then both mute and automute functions are available. if mute is not driven, automuted appears as a weak output (10k source impedance) so can be used to drive external mute circuits. input format selection in hardware mode, pins 16 and 17 become input controls for selection of input data format type and input data word length (see table 11). i 2 s mode is designed to support any word length provided enough bit clocks are sent. ml/i2s mc/iwl input data mode 0 0 16-bit right justified 0 1 20-bit right justified 1 0 24-bit right justified 1 1 i 2 s mode table 11 control of input data format type and input data word length md/dm de-emphasis in hardware mode, pin 18 becomes an input control for selection of de-emphasis filtering to be applied (see table 12). md/dm de-emphasis mode 0 de-emphasis off 1 de-emphasis on table 12 de-emphasis control
WM8756 advanced information ai rev 2.0 june 2002 26 dsdb mode select this pin puts the device into dsd mode when taken low. due to the nature of dsd operation only a single software controlled function is available in this mode. this is the pdwn bit. dsdb dsd mode 0 device in dsd mode 1 device in normal pcm operation table 13 dsd mode control dsd digital audio interface dsd mode is selected by taking the dsdb pin low. in this mode the internal digital filters are by-passed, and the already modulated bitstream data is applied directly to the switched capacitor dac filter where it is converted and low-pass filtered. two formats are supported for data transfer, normal or ph ase modulated. in normal mode, dsd data is simply clocked into the device using the rising edge of the 64fs dsdclk64 signal (see figure 3). in phase modulation mode, the data is supplied in manchester encoded form (a bit transition occurs during every data bit, which shapes the spectral energy minimising corruption of the analogue outputs). a secondary clock dsdclk128, at 128fs is used to simplify data recovery, the data simply being clocked with the falling edge of dsdclk128 when dsdclk64 is low (see figure 4). operation of ph ase modulated mode is auto-detected by the presence of a clock signal on the dsdclk128 pin. dsd clocks are either inputs (when dmslv = ? 0 ? ) or outputs (when dmslv = ? 1 ? ). when dmslv is ? 1 ? the clocks are derived by using the scki as detailed below: dmcksel dsdclk64 dsdclk128 0 scki/4 scki/2 1 scki/6 scki/3 table 14 master/slave clock selection dmslv clocks 0 inputs 1 outputs table 15 master/slave function see figure 3 and figure 4 for details of dsd interface timing
WM8756 advanced information ai rev 2.0 june 2002 27 software control interface the software control interface uses a 3-wire serial control interface. selection of interface format is achieved by setting the state of the mode pin. mode interface format 0 software control mode 1 hardware control mode table 16 control interface mode selection 3-wire (spi compatible) serial control mode the WM8756 can be controlled using a 3-wire serial interface. md/dm is used for the program data, mc/iwl is used to clock in the program data and ml/i2s is use to latch in the program data. the 3-wire interface protocol is shown in figure 15. ml/i2s mc/iwl md/dm d6 d7 d8 a0 a1 a2 a3 a4 d1 d2 d3 d4 d5 d0 a5 a6 figure 15 3-wire serial interface notes: 1. a[6:0] are control address bits 2. d[8:0] are control data bits
WM8756 advanced information ai rev 2.0 june 2002 28 register map there are 9 registers with 9 bits per register. these can be controlled using the control interface.table 22 below gives an ove rview of all the WM8756 control registers. details of each register ? s function are summarised on the following pages (table 23). a6 a5 a4 a3 a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 m0 0 0 0 0 0 0 0 update l0a7 l0a 6 l0a 5 l0a 4 l0a 3 l0a 2 l0a 1 l0a 0 m1 0 0 0 0 0 0 1 update r0a7 r0a 6 r0a 5 r0a 4 r0a 3 r0a 2 r0a 1 r0a 0 m2 0 0 0 0 0 1 0 pl3 pl2 pl1 pl0 izd atc pdwn deemph mute m3 0 0 0 0 0 1 1 rev2 rev1 rev0 iwl1 iwl0 bcp lrp fmt1 fmt0 m4 0 0 0 0 1 0 0 update l1a7 l1a 6 l1a 5 l1a 4 l1a 3 l1a 2 l1a 1 l1a 0 m5 0 0 0 0 1 0 1 update r1a7 r1a 6 r1a 5 r1a 4 r1a 3 r1a 2 r1a 1 r1a 0 m6 0 0 0 0 1 1 0 update l2a7 l2a 6 l2a 5 l2a 4 l2a 3 l2a 2 l2a 1 l2a 0 m7 0 0 0 0 1 1 1 update r2a7 r2a 6 r2a 5 r2a 4 r2a 3 r2a 2 r2a 1 r2a 0 m8 0 0 0 1 0 0 0 update masta7 masta 6 masta 5 masta 4 masta 3 masta 2 masta 1 masta 0 m9 0 0 0 1 0 0 1 0 0 0 0 0 0 0 zcd 2spd table 17 register map
WM8756 advanced information ai rev 2.0 june 2002 29 register address bit label default description 7:0 l0a[7:0] 11111111 (0db) attenuation level of left channel dacl0 in 0.5db steps, see table 10 attenuation control levels. 0000000 attenuation dacl0 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl0 in intermediate latch (no change to output) 1: store dacl0 and update attenuation on all channels. 7:0 r0a[7:0] 11111111 (0db) attenuation level of right channel dacr0 in 0.5db steps, see table 10 attenuation control levels. 0000001 attenuation dacr0 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr0 in intermediate latch (no change to output) 1: store dacr0 and update attenuation on all channels. 0 mute 0 left and right dacs soft mute control 0: no mute 1: mute 1 deemph 0 de-emphasis control 0: normal response (see figure 16 - figure 19) 1: de-emphasis response (see figure 20 - figure 25) 2 pdwn 0 left and right dacs power-down control 0: all dacs running, output is active 1: all dacs in power saving mode, output muted 3 atc 0 attenuator control 0: all dacs use attenuations as programmed. 1: right chan. dacs use corresponding left dac attenuations 4 izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect disabled 1: infinite zero detect enabled dac output control pl[3:0] left output right output pl[3:0] left output right output 0000 mute mute 1000 mute right 0001 left mute 1001 left right 0010 right mute 1010 right right 0011 (l+r)/2 mute 1011 (l+r)/2 right 0100 mute left 1100 mute (l+r)/2 0101 left left 1101 left (l+r)/2 0110 right left 1110 right (l+r)/2 0000010 dac control 8:5 pl[3:0] 1001 0111 (l+r)/2 left 1111 (l+r)/2 (l+r)/2
WM8756 advanced information ai rev 2.0 june 2002 30 register address bit label default description 1:0 fmt[1:0] 00 interface format select 00: right justified mode 01: left justified mode 10: i2s mode 11: dsp mode lrcin polarity or lrcin phase 2 lrp 0 left justified / right justified / i2s 0: standard lrcin polarity 1: inverted lrcin polarity dsp mode 0: dsp early mode 1: dsp late mode 3 bcp 0 bckin polarity 0: normal (din[2:0] and lrcin sampled on rising edge) 1: inverted (din[2:0] and lrcin sampled on falling edge) 5:4 iwl[1:0] 0 input word length 00: 16-bit mode 01: 20-bit mode 10: 24-bit mode 11: 32-bit mode (not supported in right justified mode) 0000011 interface control 8:6 rev[2:0] 000 controls the output phase of the three stereo channels 1 in bit 6 reverses the phase of data output on out0l/r. 1 in bit 7 reverses the phase of data output on out1l/r. 1 in bit 8 reverses the phase of data output on out2l/r. 7:0 l1a[7:0] 11111111 (0db) attenuation level of left channel dacl1 in 0.5db steps, see table 10 attenuation control levels. 0000100 attenuation dacl1 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl1 in intermediate latch (no change to output) 1: store dacl1 and update attenuation on all channels. 7:0 r1a[7:0] 11111111 (0db) attenuation level of right channel dacr1 in 0.5db steps, see table 10 attenuation control levels. 0000101 attenuation dacr1 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr1 in intermediate latch (no change to output) 1: store dacr1 and update attenuation on all channels. 7:0 l2a[7:0] 11111111 (0db) attenuation level of left channel dacl2 in 0.5db steps, see table 10 attenuation control levels. 0000110 attenuation dacl2 8 update not latched controls simultaneous update of all attenuation latches 0: store dacl2 in intermediate latch (no change to output) 1: store dacl2 and update attenuation on all channels. 7:0 r2a[7:0] 11111111 (0db) attenuation level of right channel dacr2 in 0.5db steps, see table 10 attenuation control levels. 0000111 attenuation dacr2 8 update not latched controls simultaneous update of all attenuation latches 0: store dacr2 in intermediate latch (no change to output) 1: store dacr2 and update attenuation on all channels. 7:0 masta[7:0] 11111111 (0db) attenuation level of all channels in 0.5db steps. see table 10 attenuation control levels 0001000 master attenuation (all channels) 8 update not latched controls simultaneous update of all attenuation latches 0: store masta[7:0] in all intermediate latches (no change to output) 1: store masta[7:0] and update attenuation on all channels.
WM8756 advanced information ai rev 2.0 june 2002 31 register address bit label default description 0 2spd 0 activates the split rate mode where the front channels run at 192khz and the rear four channels run at 96khz. 0: normal operation. 1: split rate operation. 0001001 extended interface control 1 zcd 0 controls the operation of the zero crossing detect mechanism which ensures that the volume is only updated on each channel when the signal passes through midrail. 0: enable zero detect. 1: disable zero detect. table 18 register map description
WM8756 advanced information ai rev 2.0 june 2002 32 dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 16 dac digital filter frequency response ? 44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 17 dac digital filter ripple ? 44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 18 dac digital filter frequency response 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 19 dac digital filter ripple 192khz
WM8756 advanced information ai rev 2.0 june 2002 33 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 20 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 21 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 22 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 23 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 24 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 25 de-emphasis error (48khz)
WM8756 advanced information ai rev 2.0 june 2002 34 dsd mode characteristics the following filter responses show the dac output frequency response in sacd or dsd mode, with and without an external 3 rd order lowpass filter. table 15 gives details of the attenuation versus frequency of the two cases. -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0 5000 10000 15000 20000 25000 gain (db) frequency (hz) chip output output and 3rd order butterworth filter figure 26 dsd mode frequency response - to 25khz -10 -8 -6 -4 -2 0 0 10000 20000 30000 40000 50000 60000 gain (db) frequency (hz) chip output output and 3rd order butterworth filter figure 27 dsd mode frequency response - to 60khz -50 -40 -30 -20 -10 0 10 0 20000 40000 60000 80000 100000 120000 gain (db) frequency (hz) chip output output and 3rd order butterworth filter figure 28 dsd mode frequency response - to 120khz -140 -120 -100 -80 -60 -40 -20 0 20 0 200000 400000 600000 800000 1e+06 gain (db) frequency (hz) chip output output and 3rd order butterworth filter figure 29 dsd mode frequency response - to 1mhz
WM8756 advanced information ai rev 2.0 june 2002 35 recommended external components dvdd dgnd agnd1 avdd1 cap c 13 c 12 agnd 44 15 WM8756 notes: 1. agnd and dgnd should be connected as close to the WM8756 as possible. 2. c 2 , c 3 , c 4 and c 12 should be positioned as close to the WM8756 as possible. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. avdd2 agnd2 gr0 c 3 c 4 c 5 c 2 dvdd c 1 out0r 34 c 6 out0l c 7 ac-coupled out0r/l to external lpf 36 avdd agnd gr1 gr2 out1r 30 c 8 out1l c 9 ac-coupled out1r/l to external lpf 32 out2r 25 c 10 out2l c 11 ac-coupled out2r/l to external lpf 27 40 21 28 29 + 35 31 26 + + + + + + 23 + + 45 scki 46 bckin 47 lrcin 1 din1 2 din2 audio pcm data i/f 48 din0 3 dsd0 4 dsd1 5 dsd2 7 dsd4 8 dsd5 audio dsd data i/f 6 dsd3 9 dsdclk64 ml/i2s software i/f or hardware control pins 20, 22, 24, 37-39 and 41are no connects dsdclk128 10 agnd3 11 mode 12 mute dgnd 16 17 mc/iwl 18 md/dm 14 dsdb 13 lrcin2 19 csb 33 dmslv 42 dmcksel 43 figure 30 external components diagram recommended external components values component reference suggested value description c1 and c5 10 f de-coupling for dvdd and avdd. c2 to c4 0.1 f de-coupling for dvdd and avdd. c6 to c11 10 f output ac coupling caps to remove midrail dc level from outputs. c12 0.1 f c13 10 f reference de-coupling capacitors for cap pin. table 19 external components description
WM8756 advanced information ai rev 2.0 june 2002 36 suggested analogue low pass post dac filters for pcm operation, the low out of band noise from the WM8756 means that a low order post dac filter can be used such as 2 nd order salen and key type. external 2nd orderlpf x2 for stereo operation 680pf - + 7.5k ? 1000pf 1.8k ? filtered analogue output outnr outnl 10k ? 10k ? figure 31 second order active rc low pass filter for sacd operation a 3 rd order filter may be used to meet scarlet book standards (-3db point at maximum 50khz, minimum 30db attenuation at 100khz) when combined with the filter response of the internal fir filter. such a filter may be built using a single opamp in similar fashion to the second order filter above, so costing little extra to implement. the same filter may also be used very satisfactorily for pcm operation. external 3rd orderlpf x2 for stereo operation 100pf - + 10k ? 1500pf 10k ? 680pf 10k ? filtered analogue output outnr outnl 10k ? 10k ? figure 32 third order active rc low pass filter recommended applications audio data carrier e.g. dvd, sacd tm dsd decoder pcm decoder e.g. ac-3, dts din0 din2 din1 bckin lrcin dsd0 dsd2 dsd1 dsdclk64 dsd3 dsd5 dsd4 dsdclk128 scki WM8756 6-channel dac front left surround left lfe centre surround right front right figure 33 combined pcm and dsd circuit configuration
WM8756 advanced information ai rev 2.0 june 2002 37 cxd2753r WM8756 bckao phrefo dsal dsar dsdclk128 dsdclk64 dsd1 dsd0 dsd3 dsd2 dsd5 dsd4 dsac dsasw dsals dsars figure 34 connection of WM8756 as slave to sony 6-ch dsd decoder chip in normal mode to use the WM8756 with the sony cxd2753r there are several configuration options: 1. in dsd mode if the WM8756 is being run in normal mode as a slave device the only clock input which the WM8756 requires is dsdclk64, this should be connected to the bckao pin of the cxd2753r. in this bckao should be a falling edge set as illustrated on page 20 of the cxd2753r datasheet (rev pe01704-ps). 2. in dsd mode, if the WM8756 is being run in ph ase modulation m ode as a slave device the clock inputs which the WM8756 requires are dsdclk64 and dsdclk128. dsdclk64 and dsdclk128 should be connected to phrefo and bckao respectively on the cxd2753r. in phase modulation mode phase 2 should be selected for the phrefo clock and bckao should be a rising edge set, as illustrated on page 20 of the cxd2753r datasheet (rev pe01704-ps). ? to run the WM8756 in dsd mode but as a master sclk must be present on the device. ? if the device is intended to be used for both pcm and dsd data in either master or sl ave mode sclk can be present on the WM8756 at all times as this pin is ignored by the WM8756 when it is not required.
WM8756 advanced information ai rev 2.0 june 2002 38 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 ms-026, variation = abc. refer to this specification for further details. dm004.c ft: 48 pin tqfp (7 x 7 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ----- 0.20 d 9.00 bsc d 1 7.00 bsc e 9.00 bsc e 1 7.00 bsc e 0.50 bsc l 0.45 0.60 0.75 4 0 o 3.5 o 7 o tolerances of form and position ccc 0.08 ref: jedec.95, ms-026 25 36 e b 12 1 d1 d e1 e 13 24 37 48 a a2 a1 seating plane ccc c -c- 4 c l
WM8756 advanced information ai rev 2.0 june 2002 39 revision history revision originator change date history 2.0 jmacd 06/06/02 absolute max ratings: updated device description: page 20. change to table.
WM8756 advanced information ai rev 2.0 june 2002 40 important notice wolfson microelectronics ltd (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, tha t information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the ti me of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm ? s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual proper ty right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm ? s publication of information regarding any third party ? s products or services does not constitute wm ? s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this informati on with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm ? s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics ltd 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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